The present invention relates to a method for manufacturing a capacitor of a semiconductor device to remove a capacitor oxide film without collapse of a lower electrode.
Due to rapid distribution of information media such as computers, semiconductor devices, such as semiconductor memory devices have been rapidly developed. Such semiconductor devices are required to have a high operation speed and a high storage capacity. Process equipment or process technology for manufacturing these semiconductor devices has been required to provide improved integration, reliability and electric characteristics for data access with low manufacturing cost.
As a semiconductor device becomes highly integrated, a length and a width of a gate line of a transistor, a dielectric film thickness of a gate line, and a junction depth of source/drain are all reduced. As a result, a channel region of a peripheral circuit is also reduced.
As the device is smaller by integration of the semiconductor memory device, it is difficult to manufacture a capacitor for securing sufficient capacitance. In order to increase a capacitance value, a material having a high dielectric constant is used, a height of a storage electrode is increased or a surface of a capacitor is increased. Recently, a cylinder type capacitor whose inner and outer regions are used as a node region has been widely used more than a concave type capacitor whose inner surface of the capacitor is used as a node region.
The method for manufacturing the three-dimensional cylinder type capacitor may include forming an insulating layer having a contact plug for a lower electrode over a semiconductor substrate, depositing a capacitor oxide film over the insulating layer, dry-etching the capacitor oxide film to form a trench for the lower electrode; forming a lower electrode in the trench, and performing a wet dip-out process using a wet chemical to remove a capacitor oxide film.
When a capacitor dielectric is subsequently deposited on the resultant structure, moisture penetrated between the lower electrodes while the wet dip-output process is dried. As a result, a surface tension between the lower electrodes occurs, thereby generating a leaning phenomenon where the lower electrode is collapsed to cause a bridge.
When a width of the lower electrodes is increased in order to prevent collapsing of the lower electrodes, the height of the lower electrode becomes higher for maintaining or improving capacitance. As a result, an aspect ratio of the lower electrode is not reduced again causing the leaning phenomenon of the lower electrode.
In order to prevent the leaning phenomenon, a nitride floating pattern is formed over the lower electrode so that neighboring lower electrodes are connected with each other as a supporting layer.
FIGS. 1a through 1c are diagrams illustrating a conventional method for manufacturing a capacitor.
Referring to FIG. 1a, an insulating film (not shown), a capacitor oxide film (not shown) and a nitride film (not shown) are formed over a semiconductor substrate 11 including a contact plug (not shown). A first photoresist pattern (not shown) is formed over the nitride film (not shown). The insulating film, the capacitor oxide film, the nitride film are etched with the first photoresist pattern as an etching mask to form an insulating film pattern 12, a capacitor oxide film pattern 13, a nitride floating pattern 14 and a contact hole (not shown) for lower electrode that exposes the contact plug. A conductive layer is formed in the contact hole to form a lower electrode 15. A capping oxide film 16, an amorphous carbon layer 17, an antireflection film 18 and a second photoresist pattern 19 are sequentially formed over the lower electrode 15 and the nitride floating pattern 14. The second photoresist pattern has (a) a hole pattern where sidewalls of the neighboring lower electrode are overlapped in a diagonal direction and (b) a line & space pattern where sidewalls of the neighboring lower electrode are overlapped in a straight line direction.
Referring to FIG. 1b, the capping oxide film 16, the amorphous carbon layer 17 and the antireflection film 18 are etched with the second photoresist pattern 19 as an etching mask until the nitride film floating pattern 14 is exposed to form a stack pattern comprising an amorphous carbon pattern 17-1 and a capping oxide pattern 16-1.
Referring to FIG. 1c, the nitride floating pattern 14 is removed with the stack pattern as an etching mask until the capacitor oxide film pattern 13 is exposed. The capping oxide pattern 16-1 and the amorphous carbon pattern 17-1 are removed during the etching process. A washing process is performed to remove the exposed capacitor oxide film 13, thereby exposing the lower electrode 15. A zirconium-aluminum-zirconium (ZAZ) layer 20 is coated by an island type (see FIG. 2a) and by a line type (see FIG. 2b) over the exposed lower electrode 15.
This method requires a photo mask process for forming the second photoresist pattern 19 in order to remove the capacitor oxide film 13 as shown in FIG. 1a. Therefore, the manufacturing cost increases. Moreover, it may not be possible to perform a ZAZ coating process with a uniform thickness on the lower electrode, because the nitride floating pattern remains over the lower electrode. As a result, it is difficult to obtain a capacitor having uniform charge capacity.